1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having a reduced package contour, a reduced mounting area, and a reduced cost.
2. Description of the Related Art
In the fabrication of semiconductor devices, it has been customary to separate semiconductor chips from a wafer by dicing, fixing the semiconductor chips to a lead frame, sealing the semiconductor chips fixed to the lead frame with a mold and a synthetic resin according to a transfer molding process, and dividing the sealed semiconductor chips into individual semiconductor devices. The lead frame comprises a rectangular or hooped frame. A plurality of semiconductor devices are simultaneously sealed in one sealing process.
FIG. 1 of the accompanying drawings illustrates a conventional transfer molding process. In the conventional transfer molding process, a lead frame 2 to which semiconductor chips 1 are fixed by die bonding and wire bonding is placed in a cavity 4 defined by upper and lower molds 3A, 3B. Epoxy resin is then poured into the cavity 4 to seal the semiconductor chips 1. After the transfer molding process, the lead frame 2 is cut off into segments containing the respective semiconductor chips 1, thus producing individual semiconductor devices. For more details, reference should be made to Japanese laid-open patent publication No. 05-129473, for example.
Actually, as shown in FIG. 2 of the accompanying drawings, the lower mold 3B has a number of cavities 4a-4f, a source 5 of synthetic resin, a runner 6 connected to the source 5 of synthetic resin, and gates 7 for pouring the synthetic resin from the runner 6 into the cavities 4a-4f. The cavities 4a-4f, the source 5 of synthetic resin, the runner 6, and the gates 7 are all in the form of recesses and grooves define (in the surface of the lower mold 3B. If the lead frame 2 is of a rectangular shape, then ten semiconductor chips 1 are mounted on one lead frame, and the lower mold 3B has ten cavities 4, ten gates 7, and one runner 6 per lead frame. The entire lower mold 3B has as many as cavities 4 as necessary for twenty lead frames 2, for example.
FIG. 3 of the accompanying drawings shows a semiconductor device fabricated by the conventional transfer molding process. As shown in FIG. 3, a semiconductor chip 1 containing components such as transistors is fixedly mounted on an island 8 of a lead frame by a bonding material 9 such as solder. The semiconductor chip 1 has electrode pads connected to leads 10 by wires 11, and has its peripheral portions covered with a molded body 12 of synthetic resin which is defined in shape by the cavity 4. The leads 10 have respective distal ends projecting out of the molded body 12 of synthetic resin.
In the conventional semiconductor package shown in FIG. 3, since the leads 10 for connection to external circuits project from the molded body 12 of synthetic resin, dimensions of the package that extend up to the projecting distal ends of the leads 10 need to be considered as covering a mounting area of the package. Therefore, the mounting area of the package is much larger than the contour of the molded body 12 of synthetic resin.
Furthermore, according to the conventional transfer molding process, since the molded body 12 of synthetic resin is hardened while it is being placed under pressure, the synthetic resin is also hardened in the runner 6 and the gates 7, and the hardened synthetic resin in the runner 6 and the gates 7 has to be thrown away. Because the gates 7 are required for respective individual semiconductor devices to be fabricated, the synthetic resin is not utilized highly efficiently, but the number of semiconductor devices that can be fabricated is small relatively to the amount of synthetic resin consumed.
It is therefore an object of the present invention to provide a semiconductor device having a small size with relatively small mounting area.
Another object of the present invention is to provide a method of fabricating a semiconductor device relatively inexpensively.
According to the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of preparing a board with a plurality of device carrier areas thereon, fixing semiconductor chips respectively to the device carrier areas, covering the semiconductor chips fixed to the device carrier areas with a common resin layer, flattening a surface of the common resin layer, applying a dicing sheet to the flattened surface of the common resin layer, and separating the board and the common resin layer into segments including the device carrier areas thereby to produce individual semiconductor devices by dicing from a back of the board.
The method may further comprise the step of placing an electrode pattern serving as external electrodes of the semiconductor chips on the back of the board, the electrode pattern being spaced inwardly from dicing lines along edges of the segments so as to be kept out of contact with a dicing blade along the dicing lines.
The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate a preferred embodiment of the present invention by way of example.